Publications

Here is a list of selected conference proceedings, journal papers, and materials related to our products and services. Most of them have been published before launching Device Lab Inc.

Conference proceedings

      1. K. Ohmori, A. Shinoda, K. Kawai, Z. Wei, T. Mikawa, and R. Hasunuma
        “Reduction of Cycle-to-Cycle Variability in ReRAM by Filamentary Refresh”
        VLSI Symposium on Technology, June 5-8, 2017, Kyoto, Japan.
      2. Kenji Ohmori, Ryu Hasunuma, Satoshi Yamamoto, Yoshinori Tamura, Hao Jiang, Noboru Ishihara, Kazuya Masu, and Keisaku Yamada
        “Application of Low-Noise TIA ICs for Novel Sensing of MOSFET Noise up to the GHz Region”
        VLSI Symposium on Circuits, June 11-14, 2013, Kyoto, Japan.
      3. Kenji Ohmori, Ryu Hasunuma, Wei Feng, and Keisaku Yamada
        “Continuous characterization of MOSFET from low-frequency noise to thermal noise using a novel measurement system up to 100 MHz”
        VLSI Symposium on Technology, June 12-14, 2012, Hawaii, USA.
      4. Kenji Ohmori, Ryu Hasunuma, and Keisaku Yamada
        “Development of a Novel System for Characterizing MOSFET Noise in Higher Frequency Regimes”
        International Conference on Microelectronic Test Structures (ICMTS), March 19-22, 2012, San Diego, California, USA.
      5. W. Feng, R. Hettiarachchi, Y. Lee, S. Sato, K. Kakushima, M. Sato, K. Fukuda, M. Niwa, K. Yamabe, K. Shiraishi, H. Iwai, and K. Ohmori
        “Fundamental origin of excellent low-noise property in 3D Si-MOSFETs ~ Impact of charge-centroid in the channel due to quantum effect on 1/f noise ~”
        International Electron Devices Meeting (IEDM), Washington DC, USA, Dec. 5-7, 2011.
      6. K. Ohmori, W. Feng, S. Sato, R. Hettiarachchi, M. Sato, T. Matsuki, K. Kakushima, H. Iwai, and K. Yamada
        “Direct Real-Time Observation of Channel Potential Fluctuation Correlated to Random Telegraph Noise of Drain Current Using Nanowire MOSFETs with Four-Probe Terminals”
        VLSI Symposium on Technology, Kyoto, Japan, June 14-16, 2011.
      7. K. Ohmori, T. Matsuki, D. Ishikawa, T. Morooka, T. Aminaka, Y. Sugita, T. Chikyow, K. Shiraishi, Y. Nara, K. Yamada
        “Impact of Additional Factors in Threshold Voltage Variability of Metal/High-k Gate Stacks and Its Reduction by Controlling Crystalline Structures and Grains in the Metal Gates”
        International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 15-17, 2008.
      8. K. Ohmori, T. Chikyow, T. Hosoi, H. Watanabe, K. Nakajima, T. Adachi, A. Ishikawa, Y. Sugita, Y. Nara, Y. Ohji, K. Shiraishi, K. Yamabe, K. Yamada
        “Wide Controllability of Flatband Voltage by Tuning Crystalline Microstructures in Metal Gate Electrodes”
        International Electron Devices Meeting (IEDM), Washington DC, USA, Dec. 10-12, 2007.

      Journal papers

      1. W. Feng, H. Shima, K. Ohmori, H. Akinaga
        “Investigation of switching mechanism in HfOx-ReRAM under low power and conventional operation modes”
        Scientific Reports 6 (2016) Article number: 39510.
      2. W. Feng, C. M. Dou, M. Niwa, K. Yamada, K. Ohmori
        “Impact of Random Telegraph Noise Profiles on Drain-Current Fluctuation during Dynamic Gate Bias”
        IEEE Electron Device Letters 35 (2014) pp. 3-5.

      Press releases

      1. 抵抗変化型メモリの書き換えばらつき抑制を実現
        (2017年6月、筑波大学)PDF
      2. 抵抗変化メモリーの挙動を電流ノイズから解明 - 不揮発性メモリーの用途拡大へ向けて –
        (2017年1月、産業技術総合研究所・筑波大学)PDF
      3. 独自技術の雑音プローブに開発したICを搭載し、電子デバイスの雑音特性を広帯域で計測可能に
        (2013年6月、筑波大学)PDF
      4. 立体構造トランジスタのドレイン電流雑音の低減機構を明らかにし、静かなトランジスタ構造実現の設計指針を開発 ー 量子閉じ込めによるチャネルの電化中心制御に鍵 ー
        (2011年12月、筑波大学)PDF

      Others

      1. 大毛利健治、山田啓作
        「MOSFETの雑音特性を計測する新手法を開発」
        日経エレクトロニクス 2013年11月25日号 pp. 87-93.